1. Field of the Invention
This invention relates to the checking of two dual modules, which may be identical circuit cards or other identical electronic units, which are checked by comparison of signals which should be identical. This invention is related to prior co-pending application entitled "System for Checking Duplicate Logic Using Complementary Residue Codes to Achieve High Error Coverage with a Minimum of Interface Signals," Ser. No. 235,425, filed Aug. 24, 1988, in the name of Peter B. Criswell, which is assigned to Unisys Corporation, and is hereby incorporated by reference into this document.
2. Description of the Related Art
Signals from each module are compared against each either directly or through logic which encodes the outputs to reduce the number of signals which pass between the dual modules to be compared. A miscompare between such output signals can be the result of a hardware failure internal to one of the modules, or a failure external to the modules, which results in one module receiving a different value for a signal than the other receives.
In the following discussion such modules will be discussed in terms of printed circuit boards (PCB) interconnected via a backpanel. Each PCB provides the interconnect for Large Scale Integrated (LSI) circuits which are mounted on its surface and the backpanel interconnects numerous boards. If two of these boards are identical and are checked by comparison, they may receive input signals from many of the other boards. When large sections (such as an arithmetic section of a computer) are checked by comparison, they typically compare only outputs from the section, and generally check them only at the end of an instruction sequence.
The nature of comparison checking is that if a miscompare error is detected, the failure can be on either of the dual PCB, or on any of the input links into either dual module. This provides a significant problem to the customer engineer because the list of possible failing boards which can result from a miscompare error can contain many boards.
Additional techniques are required to bring this list to a manageable level. One of the easiest ways to do this, if the input signals are grouped, is to send a parity bit with them. Then the parity checker on the input register can be used to indicate whether or not any of the input signals have failed.
Another technique is to capture certain input signals and stage them so that they can be locked-up when an error is detected. This technique works well for certain types of inputs, such as instruction codes or operands, where their value has meaning only at one particular time for each instruction. When their values are captured on both boards, they are compared, and if the values are equal, it is known that the input links did not fail and the driver boards for those signals do not have to be considered for replacement. If the capture registers are not equal, the associated link isolates the failure to three boards, the two dual LSI boards and a driver board coupled to the two boards. The present invention thus is concerned with the handling of signals which, for various reasons, cannot be detected by this prior capture technique.